The present invention relates to a data transfer device. More specifically, the present invention relates to a semiconductor integrated circuit and a microcomputer containing the data transfer device, e.g., to a technology effectively used for a single-chip microcomputer having a high-speed external input/output interface circuit.
A single-chip microcomputer comprises functional blocks such as a central processing unit (CPU) as a main component, ROM (read-only memory) for storing programs, RAM (random access memory) for storing data, and an input/output circuit for data input and output. These functional blocks are formed on a single semiconductor substrate.
There is available a single-chip microcomputer that contains a direct memory access controller (DMAC) and is capable of data transfer independently of the CPU (see patent document 1). An interrupt request can activate the DMAC capable of repeat mode and block transfer mode. In a printer system, for example, the DMAC is suitable for controlling stepping motors, controlling printout data on a printer, and storing received data in memory. Such example is capable of transferring up to eight channels of data. Since the DMAC transfers data independently of the CPU but shares a bus with the CPU, a bus cycle needed for the DMAC data transfer stops CPU operations. That is to say, in response to a single activation request, the DMAC obtains a bus access right and occupies the bus between two bus cycles for reading and writing. When byte data is transferred from the RAM to the input/output circuit to increment transfer origin and destination addresses, the DMAC occupies the bus for six states of data transfer including two states for RAM access, three states for input/output circuit access, and one state for a dead cycle in the above-mentioned example. It should be noted that one state signifies once cycle of reference clock for the single-chip microcomputer or the semiconductor integrated circuit device.
When the DMA controller is connected to an external bus for the microcomputer, it is possible to perform operations of internal buses such as a ROM lead for the CPU in parallel with external bus transfer such as transferring received data to the memory by means of the external DMA controller. However, releasing the external bus access right causes a delay in recognizing an acknowledge signal or a request signal while the bus access right is exchanged. There is generated a time interval during which the microcomputer and the external DMA controller do not use the bus so as to prevent both from colliding with each other on the bus. This easily generates an overhead irrelevant to actual operations. Overheads, if occurring before and after a single data transfer, are not negligible in comparison with the time required for an actual data transfer. If a general-purpose DMA controller is used, it also provides unnecessary functions, unfavorable to cost effectiveness. Though it is possible to develop a DMA controller optimized for each system, this is apt to be disadvantageous to manufacturing costs and the like spent for the microcomputer and a different LSI chip.
The above-mentioned application (see patent document 2) by the inventors uses the on-chip configuration for an external bus DMAC that allows the microcomputer to transfer data on the external bus, enabling concurrent operations of the external bus and the microcomputer's internal bus. Concurrent operations are made available between the external bus DMAC's data transfer on the external bus and internal bus master's operations on the internal bus such as execution of instructions by the CPU using the internal bus. It is possible to simultaneously enable data transfer by the external bus DMAC on the external bus and instruction execution by the CPU using the internal bus, thus improving the microcomputer's throughput. Data can be transferred on the external bus without degrading the CPU throughput.
In short, the DMAC represented in the above-mentioned patent documents 1 and 2 is connected as a bus master to a single bus (either the internal bus or the external bus). The DMAC uses that bus to transfer data such as reading and writing. Accordingly, the DMAC continuously occupies the bus access right of the single bus during operations of accessing a source address and destination address.
By contrast, patent document 3 describes an example of providing buffer memory capable of reading or writing via interfaces provided correspondingly to two different data processing devices. There is provided the data transfer function for exchanging data between the above-mentioned buffer memory and the data processing devices corresponding to the two interfaces. In this case, data is transferred from peripheral processing devices to the buffer memory via the first interface. Further, data is transferred from the buffer memory to the main memory via the second interface. These two types of data transfers are performed independently. A request to transfer data is also issued independently.
[Patent document 1]
Japanese Unexamined Patent Publication No. Hei 5(1993)-307516A
[Patent document 2]
Japanese Unexamined Patent Publication No. 2000-235560
[Patent document 3]
Japanese Unexamined Patent Publication No. Hei 5(1993)-2557